Parallelizing the Murφ verifier

Formal Methods in System Design

Volumn 18, Issue 2, 2001, Pages 117-129

  Stern, Ulrich ^a   Dill, David L ^a  

^a Stanford University   (United States)

Author keywords

Explicit state enumeration; Message passing; Parallel verification

Indexed keywords

ERROR ANALYSIS; NETWORK PROTOCOLS; OPTIMIZATION; PARALLEL ALGORITHMS; PARALLEL PROCESSING SYSTEMS; PROBABILITY; QUEUEING NETWORKS;

EXPLICIT STATE ENUMERATION; MESSAGE PASSING; PARALLEL VERIFICATION;

FORMAL LOGIC;

EID: 0035278979     PISSN: 09259856     EISSN: None     Source Type: Journal    
DOI: 10.1023/A:1008771324652     Document Type: Article

References (28)

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