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Volumn 45, Issue 3, 2001, Pages 511-517
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An analytical method for the thermal layout optimisation of multilayer structure solid-state devices
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Author keywords
Electro thermal modelling; Solid state devices; Thermal design optimisation
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Indexed keywords
CURRENT VOLTAGE CHARACTERISTICS;
DEGRADATION;
EMBEDDED SYSTEMS;
HEAT TRANSFER;
HIGH ELECTRON MOBILITY TRANSISTORS;
MESFET DEVICES;
MOSFET DEVICES;
MULTILAYERS;
OPTIMIZATION;
SEMICONDUCTING GALLIUM ARSENIDE;
SEMICONDUCTOR DEVICE MODELS;
SILICON ON INSULATOR TECHNOLOGY;
THERMAL CONDUCTIVITY OF SOLIDS;
ELECTRO-THERMAL MODELING;
MULTILAYER STRUCTURE SOLID-STATE DEVICES;
HETEROJUNCTIONS;
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EID: 0035275938
PISSN: 00381101
EISSN: None
Source Type: Journal
DOI: 10.1016/S0038-1101(00)00282-3 Document Type: Article |
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Times cited : (8)
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References (19)
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