Fast and accurate timing characterization using functional information

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 20, Issue 2, 2001, Pages 315-331

  Yalcin, Hakan ^a,b   Mortazavi, Mohammad ^b   Palermo, Robert ^b   Bamji, Cyrus ^c   Sakallah, Karem A ^a,d   Hayes, John P ^a,d  

^a IEEE   (United States)

^b CADENCE DESIGN SYSTEMS   (United States)

^c Canesta Inc   (United States)

^d UNIVERSITY OF MICHIGAN   (United States)

Author keywords

Delay estimation; Mode analysis; Modeling; Timing characterization; Timing verification

Indexed keywords

DEEP SUBMICROMETER INTEGRATED CIRCUIT; DELAY ESTIMATION; MODE DEPENDENT CHARACTERIZATION METHOD; TIMING VERIFICATION;

ALGORITHMS; CALCULATIONS; DELAY CIRCUITS; ELECTRIC NETWORK TOPOLOGY; MATHEMATICAL MODELS; MICROPROCESSOR CHIPS; SEQUENTIAL CIRCUITS;

INTEGRATED CIRCUIT LAYOUT;

EID: 0035248583     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.908474     Document Type: Article

References (20)

1. Timing analysis of combinational circuits using ADDs
2. Timing analysis using functional relationships
3. Path sensitization in critical path problem
4. Depth and delay in a network
5. Unveiling the ISCAS-85 benchmarks: A case study in reverse engineering
6. Hierarchical functional timing analysis
7. Approximate timing analysis of combinational circuits under the XBD0 model
8. Delay models and exact timing analysis
9. Verification of timing constraints on large digital systems
10. Analysis and design of latch-controlled synchronous digital circuits
11. Performance and testability interactions in logic synthesis
12. Functional timing optimization
13. Efficient and robust test generation-based timing analysis
14. Hierarchical timing analysis using conditional delays
15. Approximate timing analysis for datapath circuits
16. Event propagation conditions in circuit delay computation
17. Functional timing analysis for IP characterization
18. Timing abstraction of intellectual property blocks