CALiBeR: A software pipelining algorithm for clustered embedded VLIW processors

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers

Volumn , Issue , 2001, Pages 112-118

  Akturan, C ^a   Jacome, M F ^a  

^a The University of Texas at Austin   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER SOFTWARE; DATA STORAGE EQUIPMENT; EMBEDDED SYSTEMS;

SOFTWARE PIPELINING ALGORITHMS;

VERY LONG INSTRUCTION WORD ARCHITECTURE;

EID: 0035208942     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (23)

1. Register organization for media processing
2. Retiming synchronous circuitry
3. Iterative modulo scheduling an algorithm for software pipelining loops
4. RS-FDRA: A register sensitive software pipelining algorithm for embedded VLIW processors
5. FDRA: A software pipelining algorithm for embedded VLIW processors
6. Exhaustive scheduling and retiming of digital signal processing systems
7. Force directed scheduling for the behavioral synthesis of ASIC's
8. High quality operation binding for clustered VLIW datapaths
9. High level DSP synthesis using MARS design system
10. An effective methodology for functional pipelining
11. Loop optimization in register-transfer scheduling for DSP-systems
12. Resource-constrained software pipelining
13. Rotation scheduling: A loop pipelining algorithm
14. Retiming for scheduling
15. Lifetime-sensitive modulo scheduling
16. Minimizing register requirements of a modulo schedule via optimum stage scheduling
17. Minimizing register requirements under resource-constrained rate-optimal software pipelining
18. Stage scheduling: A technique to reduce the register requirements of a modulo schedule
19. Swing modulo scheduling: A lifetime sensitive approach
20. Unified assign and schedule: A new approach to scheduling for clustered register file microarchitectures
21. Distributed modulo scheduling
22. Instruction scheduling for clustered VLIW architectures