An area-efficient iterative modified-booth multiplier based on self-timed clocking

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 2001, Pages 511-512

  Shin, M C ^a   Kang, S H ^a   Park, I C ^a  

^a Korea Advanced Institute of Science and Technology (KAIST)   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC CLOCKS; ITERATIVE METHODS; LOGIC GATES;

SELF TIMED CLOCKING;

DIGITAL SIGNAL PROCESSING;

EID: 0035189705     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)

1. SPIM: A pipelined 64×64-bit iterative multiplier
2. High-speed CMOS circuit technique
3. A regular layout structured multiplier based on weighted carry-save adders