On-line integrity monitoring of microprocessor control logic

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 2001, Pages 314-319

  Kim, S ^a   Somani, A K ^a  

^a Iowa State University of Science and Technology   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CACHE MEMORY; ERROR CORRECTION; REDUNDANCY; VLSI CIRCUITS;

MICROPROCESSOR CONTROL LOGIC;

MICROPROCESSOR CHIPS;

EID: 0035177175     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (13)

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10. REESE: A method of soft error detection in microprocessors
11. A fault tolerant approach to microprocessor design
12. Embedded signature monitoring: Analysis and technique