Development of a two-step electroplating process with a long-term stability for applying to Cu metallization of 0.1 μm generation Logic ULSIs

IEEE International Symposium on Semiconductor Manufacturing Conference, Proceedings

Volumn , Issue , 2001, Pages 155-158

  Arita, K ^a   Ito, N ^a   Hosoi, N ^a   Miyamoto, H ^a  

^a NEC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

COPPER METALLURGY; ELECTROMIGRATION; ELECTROPLATING; PHYSICAL VAPOR DEPOSITION;

SEED-ENHANCEMENT STEPS;

ULSI CIRCUITS;

EID: 0035170679     PISSN: 1523553X     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)

1. Full copper wiring in a sub-0.25μm CMOS ULSI technology
2. Two-step copper electroplating technique using seed enhancement step with alkali-metal-free copper pyrophosphate bath