0.11 μm fully-depleted SOI CMOS devices with 26 nm silicon layer fabricated by bulk compatible process

IEEE International SOI Conference

Volumn , Issue , 2001, Pages 23-24

  Komatsu, H ^a   Nakayama, H ^a   Koyama, K ^a   Matsumoto, K ^a   Ohno, T ^a   Takeshita, K ^a  

^a SONY CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; INTEGRATED CIRCUIT LAYOUT; SEMICONDUCTING SILICON; TRANSMISSION ELECTRON MICROSCOPY;

BULK COMPATIBLE PROCESSES; SILICON LAYERS;

SILICON ON INSULATOR TECHNOLOGY;

EID: 0035159827     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)