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Volumn 18, Issue 1, 2001, Pages 42-49

Fault detection and location using I DD waveform analysis

Author keywords

[No Author keywords available]

Indexed keywords

AT SPEED TEST UNIT; CIRCUIT UNDER TEST; CURRENT WAVEFORM BASED ANALYSIS; FAULT DETECTION; INTEGRATOR BASED WAVEFORM COMPARISON METHOD; SOFTWARE PACKAGE HSPICE;

EID: 0035127378     PISSN: 07407475     EISSN: None     Source Type: Journal    
DOI: 10.1109/54.902821     Document Type: Article
Times cited : (28)

References (10)
  • 1
    • 0030399873 scopus 로고    scopus 로고
    • inverted c sign∞ Testing: Issues Present and Future
    • inverted c sign∞ Testing: Issues Present and Future," IEEE Design & Test of Computers, vol. 13, no. 4, 1996, pp. 61-65.
    • (1996) IEEE Design & Test of Computers , vol.13 , Issue.4 , pp. 61-65
    • Soden, J.M.1    Hawkins, C.F.2
  • 2
    • 0031699114 scopus 로고    scopus 로고
    • ∞ Waveform Analysis for Testing of Domino and Low Voltage Static CMOS Circuits
    • IEEE Computer Soc. Press, Los Alamitos, Calif.
    • ∞ Waveform Analysis for Testing of Domino and Low Voltage Static CMOS Circuits," Proc. 8th Great Lakes Symp. VLSI, IEEE Computer Soc. Press, Los Alamitos, Calif., 1998, pp. 243-248.
    • (1998) Proc. 8th Great Lakes Symp. VLSI , pp. 243-248
    • Soeleman, H.1    Somasekhar, D.2    Roy, K.3
  • 3
    • 0029214663 scopus 로고
    • Detection and Location of Faults and Defects Using Digital Signal Processing
    • IEEE Computer Soc. Press, Los Alamitos, Calif.
    • C. Thibeault, "Detection and Location of Faults and Defects Using Digital Signal Processing," 13th IEEE Int'l VLSI Test Symp., IEEE Computer Soc. Press, Los Alamitos, Calif., 1995, pp. 262-267.
    • (1995) 13th IEEE Int'l VLSI Test Symp. , pp. 262-267
    • Thibeault, C.1
  • 4
    • 0028698364 scopus 로고
    • RAFT: A Novel Program for Rapid-Fire Test and Diagnosis of Digital Logic for Marginal Delays and Delay Faults
    • IEEE Computer Soc. Press, Los Alamitos, Calif.
    • A. Chatterjee and J. Abraham, "RAFT: A Novel Program for Rapid-Fire Test and Diagnosis of Digital Logic for Marginal Delays and Delay Faults," Proc. IEEE/ACM Int'l Conf. Computer-Aided Design (ICCAD), IEEE Computer Soc. Press, Los Alamitos, Calif., 1994, pp. 340-343.
    • (1994) Proc. IEEE/ACM Int'l Conf. Computer-Aided Design (ICCAD) , pp. 340-343
    • Chatterjee, A.1    Abraham, J.2
  • 5
    • 0029471827 scopus 로고
    • inverted c sign∞ Test and Diagnosis of CMOS Circuits
    • inverted c sign∞ Test and Diagnosis of CMOS Circuits," IEEE Design & Test of Computers, vol. 12, no. 4, 1995, pp. 60-67.
    • (1995) IEEE Design & Test of Computers , vol.12 , Issue.4 , pp. 60-67
    • Isern, E.1    Figueras, J.2
  • 7
    • 0029519859 scopus 로고
    • Transient Power Supply Current Testing of Digital CMOS Circuits
    • IEEE Computer Soc. Press, Los Alamitos, Calif.
    • R.Z. Makki, S.T. Su, and T. Nagle, "Transient Power Supply Current Testing of Digital CMOS Circuits," Proc. Int'l Test Conf., IEEE Computer Soc. Press, Los Alamitos, Calif., 1995, pp. 892-901.
    • (1995) Proc. Int'l Test Conf. , pp. 892-901
    • Makki, R.Z.1    Su, S.T.2    Nagle, T.3
  • 8
    • 0026981157 scopus 로고
    • Design of ICs Applying Built-in Current Testing
    • W. Maly and M. Patyra, "Design of ICs Applying Built-in Current Testing," J. Electronic Testing: Theory & Applications, vol. 3, no. 4, 1992, pp. 397-406.
    • (1992) J. Electronic Testing: Theory & Applications , vol.3 , Issue.4 , pp. 397-406
    • Maly, W.1    Patyra, M.2
  • 9
    • 0034459843 scopus 로고    scopus 로고
    • Intrinsic Leakage in Deep Submicron ICs: Measurement Based Test Solutions
    • to be published in Dec.
    • A. Keshavarzi, K. Roy, and C. Hawkins, "Intrinsic Leakage in Deep Submicron ICs: Measurement Based Test Solutions," to be published in IEEE Trans. VLSI Systems, Dec. 2000.
    • (2000) IEEE Trans. VLSI Systems
    • Keshavarzi, A.1    Roy, K.2    Hawkins, C.3
  • 10
    • 0027189119 scopus 로고
    • Bridge Fault Simulation Strategies for CMOS ICs
    • IEEE Computer Soc. Press, Los Alamitos, Calif.
    • B. Chess and T. Larrabee, "Bridge Fault Simulation Strategies for CMOS ICs," Proc. Design Automation Conf. (DAC), IEEE Computer Soc. Press, Los Alamitos, Calif., 1993, pp. 458-462.
    • (1993) Proc. Design Automation Conf. (DAC) , pp. 458-462
    • Chess, B.1    Larrabee, T.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.