A low-power bit-serial multiplier for finite fields GF(2m)

Materials Research Society Symposium - Proceedings

Volumn 626, Issue , 2001, Pages

  Grossschadl J ^a  

^a GRAZ UNIVERSITY OF TECHNOLOGY   (Austria)

Author keywords

Bit serial multiplier architecture; Finite field arithmetic; Low power VLSI design; Smart card crypto coprocessor

Indexed keywords

GATES (TRANSISTOR); MATHEMATICAL MODELS; VLSI CIRCUITS;

FINITE FIELD ARITHMETICS;

MULTIPLYING CIRCUITS;

EID: 0035026562     PISSN: 02729172     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)