Capacitive voltage multipliers: A high efficiency method to generate multiple on-chip supply voltages

ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings

Volumn 1, Issue , 2001, Pages 508-511

  Balczewski, Ron ^a   Harjani, Ramesh ^a  

^a UNIVERSITY OF MINNESOTA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DESIGN EQUATION; HEURISTIC RULES; MULTIPLE POWER SUPPLY; PARASITIC CAPACITANCE; PARASITIC RESISTANCES; PREDICTED PERFORMANCE; SIMPLIFIED METHOD; VOLTAGE MULTIPLIERS;

ANALOG CIRCUITS; CAPACITANCE; TOPOLOGY; CAPACITORS; CMOS INTEGRATED CIRCUITS; EFFICIENCY; ELECTRIC POTENTIAL; POWER SUPPLY CIRCUITS;

DESIGN; MULTIPLYING CIRCUITS;

CAPACITIVE VOLTAGE MULTIPLIERS;

EID: 0035023759     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2001.921904     Document Type: Conference Paper

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