Layout aware retiming

Proceedings of the IEEE Great Lakes Symposium on VLSI

Volumn , Issue , 2001, Pages 25-30

  Ranjan, A ^a   Srivastava, A ^a   Karnam, V ^a   Sarrafzadeh, M ^a  

^a Monterey Design Systems   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CHIP SCALE PACKAGES; DELAY CIRCUITS; INTEGRATED CIRCUIT LAYOUT; LOGIC DESIGN; LOGIC GATES; OPTIMIZATION; SHIFT REGISTERS; TIMING CIRCUITS;

SEQUENTIAL CIRCUIT RETIMING;

SEQUENTIAL CIRCUITS;

EID: 0035022189     PISSN: 10661395     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/368122.368153     Document Type: Conference Paper

References (21)