Performance optimization of 60 nm channel length vertical MOSFETs using channel engineering

Proceedings of the IEEE International Conference on VLSI Design

Volumn , Issue , 2001, Pages 475-478

  Shrivastav, G ^a   Mahapatra, S ^a   Ramgopal Rao, V ^a   Vasi, J ^a   Anil, K G ^b   Fink, C ^b   Hansch, W ^b   Eisele, I ^b  

^a INDIAN INSTITUTE OF TECHNOLOGY BOMBAY   (India)

^b BUNDESWEHR UNIVERSITY MUNICH   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

CURRENT VOLTAGE CHARACTERISTICS; DOPING (ADDITIVES); GATES (TRANSISTOR); HOT CARRIERS; MOLECULAR BEAM EPITAXY; SEMICONDUCTOR DOPING; VLSI CIRCUITS;

CHANNEL ENGINEERING;

MOSFET DEVICES;

EID: 0035013776     PISSN: 10639667     EISSN: None     Source Type: Journal    
DOI: 10.1109/ICVD.2001.902703     Document Type: Article

References (0)