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Volumn 2, Issue , 2001, Pages 653-656

Signal activity and power consumption reduction using the logarithmic number system

Author keywords

[No Author keywords available]

Indexed keywords

EQUIVALENT-LINEAR; GAUSSIANS; INPUT DISTRIBUTIONS; LOGARITHMIC NUMBER SYSTEM; POWER CONSUMPTION REDUCTION; SIGNAL ACTIVITY;

EID: 0035013762     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2001.921155     Document Type: Conference Paper
Times cited : (8)

References (9)
  • 5
    • 0029485007 scopus 로고
    • 114 MFLOPS logarithmic number system arithmetic unit for DSP applications
    • Dec.
    • D. M. Lewis, "114 MFLOPS Logarithmic Number System arithmetic unit for DSP applications", IEEE Journal of Solid-State Circuits, vol. 30, pp. 1547-1553. Dec. 1995.
    • (1995) IEEE Journal of Solid-state Circuits , vol.30 , pp. 1547-1553
    • Lewis, D.M.1
  • 7
    • 0000440896 scopus 로고
    • Architectural power analysis: The dual bit type method
    • June
    • P. E. Landman and J. M. Rabaey, "Architectural power analysis: The Dual Bit Type method", IEEE Transactions on VLSI Systems, vol. 3, pp. 173-187, June 1995.
    • (1995) IEEE Transactions on VLSI Systems , vol.3 , pp. 173-187
    • Landman, P.E.1    Rabaey, J.M.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.