Hardware combinatorial optimization problems solver by hysteresis neural networks

ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings

Volumn 3, Issue , 2001, Pages 565-568

  Nakaguchi, T ^a   Jin'No, K ^b   Tanaka, M ^a  

^a SOPHIA UNIVERSITY   (Japan)

^b NIPPON INSTITUTE OF TECHNOLOGY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

COMBINATORIAL OPTIMIZATION PROBLEMS; HARDWARE OPTIMIZATION; NUMERICAL CALCULATION;

COMBINATORIAL OPTIMIZATION; HARDWARE; NEURAL NETWORKS; PARALLEL ARCHITECTURES; NUMERICAL METHODS; OPTIMIZATION; PARALLEL PROCESSING SYSTEMS; PROBLEM SOLVING;

HYSTERESIS; NEURAL NETWORKS;

HYSTERESIS NEURAL NETWORKS (HNN);

EID: 0035005684     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2001.921373     Document Type: Conference Paper

References (5)

1. T. Saito, M. Oikawa and K. Jin'no, "Dynamics of hysteretic neural networks", in Proc. of IEEE/ISCAS'91, pp. 1469-1472, Singapore, 1991. 5.
2. T. Nakaguchi, K. Jin'no and Mamoru Tanaka, "Hysteresis Networks for Combinatorial Optimization Problems", in Proc. of NOLTA'98, pp. 437-440, Crans-Montana, Switzerland, 1998. 9.
3. T. Nakaguchi, K. Jin'no and M. Tanaka, "Hysteresis Neural Networks for N-Queens Problems", in IEICE Trans. Fundamentals, vol. E82-A, No. 9, pp. 1851-1854, 1999
4. T. Nakaguchi, K. Jin'no and M. Tanaka, "Theoretical Analysis of Hysteresis Neural Network Solving N-Queens Problems", in Proc. of IEEE/ISCAS'99, V-555, Orlando, Fl, USA, 1999. 5.
5. T. Nakaguchi, K. Jin'no and M. Tanaka, "Hysteresis Neural Networks for Solving Traveling Salesperson Problems", in Proc. of IEEE/ISCAS 2000, III-153, Geneva, Switzerland, 2000. 5.