An area-efficient architecture for Reed-Solomon decoder using the inversionless decomposed Euclidean algorithm

ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings

Volumn 2, Issue , 2001, Pages 649-652

  Chang, Hsie Chia ^a   Lee, Chen Yi ^a  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATIONS IN COMMUNICATIONS; CORRECTION OF ERRORS; DECOMPOSED ALGORITHMS; EFFICIENT COMPUTATION; EUCLIDEAN ALGORITHMS; PROPOSED ARCHITECTURES; REED SOLOMON DECODER; STORAGE SYSTEMS;

ALGORITHMS; DECODING; COMPUTER ARCHITECTURE; ERROR CORRECTION; REED RELAYS;

COMPUTATIONAL EFFICIENCY; DECODING;

REED-SOLOMON DECODERS;

EID: 0035004781     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2001.921154     Document Type: Conference Paper

References (4)

1. E. Berlekamp, Algebraic Coding Theory. McGraw-Hill, New York, 1968.
2. H. M. Shao and I. S. Reed, "On the VLSI Design of a Pipeline Reed-Solomon Decoder Using Systolic Arrays", IEEE Transaction on Computers, vol. 37, no. 10, pp. 1273-1280, 1988.
3. Y. D. Keiichi Iwamura and H. Imai, "A Design of Reed-Solomon Decoder with Systolic-Array Structure", IEEE transactoin on Communications, vol. 44, pp. 118-122, 1995.
4. H. Chang and M. Sunwoo. "A low complexity Reed-Solomon architecture using the Euclid's algorithm", Proc. of the IEEE International Symposium on Circuits and Systems, vol. 1, pp. 513-516, 1999.