A low-cost adaptive ramp generator for analog BIST applications

Proceedings of the IEEE VLSI Test Symposium

Volumn , Issue , 2001, Pages 266-271

  Azais F ^a   Bernard, S ^a   Bertrand, Y ^a   Michel, X ^a   Renovell, M ^a  

^a UNIV MONTPELLIER   (France)

Author keywords

[No Author keywords available]

Indexed keywords

ANALOG TO DIGITAL CONVERSION; BUILT-IN SELF TEST; CAPACITORS; ELECTRIC CURRENTS; ELECTRIC POTENTIAL; INTEGRATED CIRCUIT TESTING; TIME DOMAIN ANALYSIS;

MIXED SIGNAL CIRCUITS; RAMP VOLTAGE;

RAMP GENERATORS;

EID: 0035004319     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (14)

1. Hybrid built-in self-test (HBIST) for mixed analogue/digital integrated circuits
2. T-BIST: A built-in self-test for analog circuits based on parameter translation
3. Frequency-based BIST for analog circuit testing
4. A simplified polynomial-fitting algorithm for DAC and ADC BIST
5. Built-in self-test methodology for A/D converters
6. Built-in self-test for pipeline ADCs
7. Hardware resource minimization for a histogram-based ADC BIST
8. Arbitrary-precision signal generation for bandlimited mixed-signal testing
9. An analog multi-tone signal generator for built-in self-test applications
10. Analog signal generation for built-in self-test of mixed-signal integrated circuits
11. Auto-calibrating analog timer for on-chip testing
12. On-chip analog output response compaction
13. On the development of transient response testing techniques for mixed-mode ICs
14. Analog testing with time response parameters