How to half wire lengths in the layout of cyclic shifters

Proceedings of the IEEE International Conference on VLSI Design

Volumn , Issue , 2001, Pages 339-344

  Hillebrand, M A ^a   Schurger T ^a   Seidel, P M ^a  

^a SAARLAND UNIVERSITY   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

DIGITAL ARITHMETIC; LOGIC CIRCUITS; LOGIC GATES; MATHEMATICAL MODELS; MULTIPLEXING; OPTIMIZATION; SHIFT REGISTERS;

CYCLIC SHIFTERS;

MICROPROCESSOR CHIPS;

EID: 0034998855     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (11)