SCOPUS 정보 검색 플랫폼

ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings

Volumn 1, Issue , 2001, Pages 468-471

Error analysis for time-interleaved analog channels

(2) Baiying, Yu a,b Black Jr , William C a

a Iowa State University of Science and Technology (United States)

b AGERE SYSTEMS (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMBINED CHANNELS; DIGITAL SIGNALS; GAIN AND OFFSET; HIGH-SPEED DATA CONVERTERS; PROCESSING CHANNELS; SIGNALTONOISE RATIO (SNR); TIME-INTERLEAVED; TIME-INTERLEAVED ARCHITECTURE;

SIGNAL PROCESSING; COMPUTER SIMULATION; DIGITAL SIGNAL PROCESSING; ERROR ANALYSIS; SIGNAL TO NOISE RATIO; TIMING CIRCUITS;

SIGNAL TO NOISE RATIO; ANALOG TO DIGITAL CONVERSION;

ANALOG CHANNELS;

EID: 0034995983 PISSN: None EISSN: None Source Type: Conference Proceeding
DOI: 10.1109/ISCAS.2001.921894 Document Type: Conference Paper

Times cited : (13)

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