Power reduction through work reuse

Proceedings of the International Symposium on Low Power Electronics and Design, Digest of Technical Papers

Volumn , Issue , 2001, Pages 340-345

  Talpes, E ^a   Marculescu, D ^a  

^a CARNEGIE MELLON UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BUFFER STORAGE; HEAT LOSSES; MICROPROCESSOR CHIPS; PIPELINE PROCESSING SYSTEMS;

PIPELINE STRUCTURES;

COMPUTER ARCHITECTURE;

EID: 0034878754     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/383082.383180     Document Type: Conference Paper

References (16)

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6. Energy efficient CMOS microprocessor design
7. The filter cache: An energy efficient memory structure
8. Architectural and compiler techniques for energy reduction in high performance processors
9. Power reduction through clock gating by symbolic manipulation
10. The simplescalar architectural research tool set, version 2.0
11. Wattch: A framework for architectural-level power analysis and optimizations
12. Reducing power in superscalar processor caches using subbanking, multiple line buffers and bit-line segmentation