Iterative heuristics for multiobjective VLSI standard cell placement

Proceedings of the International Joint Conference on Neural Networks

Volumn 3, Issue , 2001, Pages 2224-2229

  Sait, S M ^a   Youssef, H ^a   El Maleh, A H ^a   Minhas, M R ^a  

^a KING FAHD UNIVERSITY OF PETROLEUM AND MINERALS   (Saudi Arabia)

Author keywords

[No Author keywords available]

Indexed keywords

FUNCTIONS; FUZZY SETS; GENETIC ALGORITHMS; INTEGRATED CIRCUIT LAYOUT; ITERATIVE METHODS; OPTIMIZATION; VLSI CIRCUITS;

ALGORITHMIC PARAMETERS; ITERATIVE HEURISTICS; MULTIOBJECTIVE COST FUNCTION; MULTIOBJECTIVE STANDARD CELL PLACEMENT; TABU SEARCH;

HEURISTIC PROGRAMMING;

EID: 0034870729     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)

1. VLSI cell placement techniques
2. ESP: Placement by simulated evolution
3. Ritual: A performance-driven placement algorithm
4. PCUBE: A performance driven placement algorithm for low power design
5. GEEP: A low power genetic algorithm layout system
6. VLSI physical design automation: Theory and practice
7. CAD for low power: Status and promising directions
8. A survey of optimization techniques targeting low power VLSI circuits
9. On ordered weighted averaging aggregation operators in multicriteria decision making