Specifications and FPGA implementation of a systolic Hopfield-type associative memory

Proceedings of the International Joint Conference on Neural Networks

Volumn 1, Issue , 2001, Pages 228-233

  Mihu, I Z ^a   Brad, R ^a   Breazu, M ^a  

^a LUCIAN BLAGA UNIVERSITY OF SIBIU   (Romania)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; DIGITAL INTEGRATED CIRCUITS; FIELD PROGRAMMABLE GATE ARRAYS; LEARNING ALGORITHMS; PARALLEL PROCESSING SYSTEMS; REAL TIME SYSTEMS; SYSTOLIC ARRAYS; VLSI CIRCUITS;

PROCESSING ELEMENTS; SYSTOLIC CELLS;

NEURAL NETWORKS;

EID: 0034857172     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (14)

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6. General - Purpose systolic arrays
7. GENES IV: A bit-serial processing element for multimodel neural-network accelerator
8. Design, implementation, and test of a multimodel systolic neural-network accelerator
9. Systolic arrays: From concepts to implementation
10. Backpropagation in linear arrays - A performance analysis and optimization
11. SYNAPSE - A neurocomputer that synthesizes neural algorithms on a parallel systolic engine
12. MANTRA I: An SIMD processor array for neural computation