ESD protection strategy for sub-quarter-micron CMOS technology: Gate-driven design versus substrate-triggered design

International Symposium on VLSI Technology, Systems, and Applications, Proceedings

Volumn , Issue , 2001, Pages 232-235

  Chen, T Y ^a   Ker, M D ^a  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

CURRENT VOLTAGE CHARACTERISTICS; ELECTRIC CURRENTS; ELECTROSTATICS; GATES (TRANSISTOR); MOSFET DEVICES; SUBSTRATES;

ELECTROSTATIC DISCHARGE (ESD);

CMOS INTEGRATED CIRCUITS;

EID: 0034856208     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)

1. Process and design for ESD robustness in deep submicron CMOS technology
2. Achieving uniform NMOS device power distribution for sub-micron ESD reliability
3. Dynamic gate coupling of NMOS for efficient output ESD protection
4. Design methodology and optimization of gate-driven NMOS ESD protection circuits in submicron CMOS processes
5. Substrate triggering and salicide effects on ESD performance and protection circuit design in deep submicron CMOS processes
6. Design of cost-efficient ESD clamp circuits for the power rails of CMOS ASIC's with substrate-triggering technique
7. Novel input ESD protection circuit with substrate-triggering technique in a 0.25-μm shallow-trench-isolation CMOS technology
8. Experimental investigation on the HBM ESD characteristics of CMOS devices in a 0.35μm silicided process