Clustered VLIW architectures with predicated switching

Proceedings - Design Automation Conference

Volumn , Issue , 2001, Pages 696-701

  Jacome, Margarida F ^a   De Veciana, Gustavo ^a   Pillai, Satish ^a  

^a The University of Texas at Austin   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DATA TRANSFER; PARALLEL PROCESSING SYSTEMS; PROGRAM COMPILERS; PROGRAM PROCESSORS; SWITCHING;

COMPILER TRANSFORMATIONS; INSTRUCTIONAL LEVEL PARALLELISM (ILP);

APPLICATION SPECIFIC INTEGRATED CIRCUITS;

EID: 0034848157     PISSN: 0738100X     EISSN: None     Source Type: Journal    
DOI: 10.1109/DAC.2001.156227     Document Type: Article

References (15)

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10. Using profile information to assist classic code optimizations
11. The superblock: An effective technique for VLIW and superscalar compilation
12. Trace scheduling: A technique for global microcode compaction
13. Exploiting conditional instructions in code generation for embedded VLIW processors
14. Trace selection for compiling large C application programs to microcode