Integrated modeling methodology for core and I/O power delivery

Proceedings - Electronic Components and Technology Conference

Volumn , Issue , 2001, Pages 1107-1110

  Radhakrishnan, Kaladhar ^a   Li, Yuan Liang ^a   Pinello, William P ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

INTEGRATED CIRCUIT LAYOUT; MATHEMATICAL MODELS; MICROPROCESSOR CHIPS; SPURIOUS SIGNAL NOISE;

INTEGRATED MODELING METHOD; SWITCHING CURRENTS;

ELECTRONICS PACKAGING;

EID: 0034835193     PISSN: 05695503     EISSN: None     Source Type: Journal    
DOI: 10.1109/ECTC.2001.927961     Document Type: Article

References (3)

1. Modeling and analysis of multichip module power supply planes
2. Novel methodology for mid-frequency delta-I noise analysis of complex computer system boards and verification by measurements