A DSP based 10BaseT/100BaseTX ethernet transceiver in a 1.8V, 0.18um CMOS technology

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 2001, Pages 135-138

  Huss, S ^a   Mullen, M ^a   Gray, C T ^a   Smith, R ^a   Summers, M ^a   Shafer, J ^a   Heron, P ^a   Sawinska, T ^a   Medero, J ^a  

^a Tality Corporation   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BIT ERROR RATE; CMOS INTEGRATED CIRCUITS; DIGITAL SIGNAL PROCESSING; LOCAL AREA NETWORKS; NETWORK PROTOCOLS; PERFORMANCE; SIGNAL TO NOISE RATIO; TRANSMITTERS;

ETHERNET; MEDIA INDEPENDENT INTERFACE; SERIAL MANAGEMENT INTERFACE;

TRANSCEIVERS;

EID: 0034833074     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. Media access control parameters, physical layer, medium attachment units, and repeater for 100MB/s operation, type 100Base-T
2. A CMOS transceiver for 10 MB/s and 100 MB/s ethernet
3. A mixed-signal DFE/FFE receiver for 100base-TX applications
4. A 3V low-power 0.25um CMOS 100MB/s receiver for fast ethernet
5. Low voltage line driver topologies for 10base-T and 100base-TX ethernet
6. Timing recovery in digital synchronous data receivers