DLP+TLP processors for the next generation of media workloads

IEEE High-Performance Computer Architecture Symposium Proceedings

Volumn , Issue , 2001, Pages 219-228

  Corbal, Jesus ^a   Espasa, Roger ^a   Valero, Mateo ^a  

^a UNIVERSITAT POLITÈCNICA DE CATALUNYA   (Spain)

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH COMPRESSION; BUFFER STORAGE; HIERARCHICAL SYSTEMS; IMAGE COMPRESSION; MICROPROCESSOR CHIPS; MULTIMEDIA SYSTEMS; STANDARDS; SURFACE MOUNT TECHNOLOGY;

MOTION PICTURE EXPERT GROUP (MPEG);

PROGRAM PROCESSORS;

EID: 0034817776     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (30)