Synthesis of configurable linear feedback shifter registers for detecting random-pattern-resistant faults

Proceedings of the International Symposium on System Synthesis

Volumn , Issue , 2001, Pages 203-208

  Chen, C I H ^a  

^a Wright State University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BUILT-IN SELF TEST; FLIP FLOP CIRCUITS; OPTIMIZATION; ROM; VLSI CIRCUITS;

LINEAR FEEDBACK SHIFTER REGISTERS (LFSR);

SHIFT REGISTERS;

EID: 0034785264     PISSN: 10801820     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/500001.500051     Document Type: Conference Paper

References (13)

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5. An efficient BIST scheme based on reseeding of multiple polynomial linear feedback shift registers
6. Built-in test for circuits with scan based on reseeding of multiple-polynomial linear feed-back shift registers
7. Automated synthesis of a multiple-sequence test generator using 2-D LFSR
8. Pseudorandom testing
9. A method for pseudo-exhaustive test pattern generation
10. The pseudoexhaustive test for sequential circuits
11. Design of an efficient weighted random pattern generation system
12. A new procedure for weighted random built-in self- test