Impact analysis of process variability on digital circuits with performance limited yield

International Workshop on Statistical Metrology, Proceedings, IWSM

Volumn , Issue , 2001, Pages 60-63

  Malavasi, E ^a   Zanella, S ^a   Uschersohn, J ^a   Misheloff, M ^a   Guardiani, C ^a  

^a PDF SOLUTIONS INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CRITICAL PATH ANALYSIS; LOGIC CIRCUITS; MATHEMATICAL MODELS; MOS DEVICES; OPTIMIZATION; STATISTICAL METHODS; TIMING CIRCUITS;

INTEGRATED CIRCUIT ANALYSIS;

DIGITAL CIRCUITS;

EID: 0034783653     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

1. Primitive path delay faults: Identification and their use in timing analysis
2. Statistical timing macromodels of digital IP libraries
3. Model order-reduction of RC(L) interconnect including variational analysis
4. A method for certain nonlinear problems in least squares