Direct-mapped asynchronous finite-state machines in CMOS technology

Proceedings of the Annual IEEE International ASIC Conference and Exhibit

Volumn , Issue , 2001, Pages 105-109

  Sotiriou, C P ^a  

^a INSTITUTE OF COMPUTER SCIENCE   (Greece)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC NETWORK ANALYSIS; ENCODING (SYMBOLS); FINITE AUTOMATA; FLIP FLOP CIRCUITS; LOGIC GATES; SCHEMATIC DIAGRAMS; TRANSISTORS;

ASYNCHRONOUS CONTROL CIRCUIT DESIGN; ASYNCHRONOUS FINITE STATE MACHINE; DIRECT MAPPED CIRCUIT DESIGN;

INTEGRATED CIRCUIT LAYOUT;

EID: 0034781468     PISSN: 10630988     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)

1. Will physical scalability sabotage performance gains?
2. Deep-submicron microprocessor design issues
3. The limitations to delay-insensitivity in asynchronous circuits
4. Direct implementation of asynchronous control units
5. Four-phase micropipeline latch control circuits
6. Automatic synthesis of fast compact asynchronous circuits
7. Quantifying the complexity of superscalar processors
8. Synthesis of self-timed VLSI circuits from graph-theoretic specifications