A VLSI design of a high-speed Reed-Solomon decoder

Proceedings of the Annual IEEE International ASIC Conference and Exhibit

Volumn , Issue , 2001, Pages 316-320

  Lee, H ^a  

^a AGERE SYSTEMS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CMOS INTEGRATED CIRCUITS; CODES (SYMBOLS); DATA COMMUNICATION SYSTEMS; DECODING; ERROR CORRECTION; INTEGRATED CIRCUIT LAYOUT;

HIGH SPEED DECODER; MODIFIED EUCLIDEAN ALGORITHM; REED-SOLOMON CODES;

VLSI CIRCUITS;

EID: 0034776713     PISSN: 10630988     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

1. Forward error correction for submarine systems
2. A VLSI design of a pipeline Reed-Solomon decoder
3. On the VLSI design of a pipeline Reed-Solomon decoder using systolic arrays
4. A new scalable VLSI architecture for Reed-Solomon decoders
5. An area-efficient VLSI architecture of a Reed-Solomon decoder/encoder for digital VCRs