Performance evaluation of 3rd order sigma-delta (Σ-Δ) modulators via FPGA implementation

Proceedings of the Annual IEEE International ASIC Conference and Exhibit

Volumn , Issue , 2001, Pages 13-17

  Abeysekera, S S ^a   Charoensak, C ^a  

^a NANYANG TECHNOLOGICAL UNIVERSITY   (Singapore)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATIONAL METHODS; DECISION FEEDBACK EQUALIZERS; DEMODULATORS; DIGITAL FILTERS; FIELD PROGRAMMABLE GATE ARRAYS; MODULATORS; RECURSIVE FUNCTIONS; SHIFT REGISTERS; SIGNAL TO NOISE RATIO; VLSI CIRCUITS;

LOOK AHEAD DECISION FEEDBACK ARCHITECTURE; RECURSIVE FILTERS; SIGMA DELTA MODULATORS; SYSTEM-ON-CHIP DESIGN;

DELTA SIGMA MODULATION;

EID: 0034771096     PISSN: 10630988     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)

1. Look-ahead decision-feedback sigma-delta modulation
2. Optimum Laguerre filter design technique for sigma-delta demodulators
3. Fully sigma-delta modulation encoded FIR filters
4. Oversampling A-to-D and D-to-A converters with multistage noise shaping modulators
5. Multistage sigma-delta modulation
6. FIR filters with sigma-delta modulation encoding
7. FPGA signal processing using sigma-delta modulation
8. Design of multiplier free FIR filters using LADF sigma-delta modulator
9. Optimum sigma-delta demodulator filter implementation via FPGA