The ATLAS level-2 trigger pilot project

IEEE Nuclear Science Symposium and Medical Imaging Conference

Volumn 2, Issue , 2000, Pages

  Wickens, F ^a  

^a NONE

Author keywords

[No Author keywords available]

Indexed keywords

BUFFER STORAGE; COMPUTER SIMULATION; DATA ACQUISITION; FIELD PROGRAMMABLE GATE ARRAYS; OPTIMIZATION; PARTICLE DETECTORS;

HIGH LEVEL TRIGGER; READOUT BUFFER; REGION OF INTEREST;

COLLIDING BEAM ACCELERATORS;

EID: 0034593907     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (28)

1. ATLAS DAQ, EF, LVL2 and DCS Technical Progress Report, CERN-LHCC-98-16
2. E. Gamma, R. Jonson, J. Vlissides, Design patterns, Addison-Wesley (1995)
3. Message Passing Interface (MPI), http://www-unix.mcs.anl.gov/mpi/
4. M. Boosten et al., Fine-grain parallel processing on commodity platforms, in Architectures, Languages and Techniques, Ed. B. M. Cook, IOS Press, pp. 263-276
5. Running the ATLAS second level trigger software on a large commercial cluster, ATLAS internal note, ATL-DAQ-2000-024 (2000).
6. Paper modelling of the ATLAS LVL2 trigger system, ATLAS internal note, ATL-DAQ-2000-030 (2000)
7. Computer modelling of the ATLAS LVL2 trigger, ATLAS internal note, ATL-COM-DAQ-2000-031 (2000)
8. M. Abolins et al., Commodity Multi-processor Systems in the ATLAS Level-2 Trigger, NSS 2000 Paper 92.
9. Options for the ROB complex, ATLAS internal note, ATL-DAQ-2000-027 (2000)
10. A SHARC based ROB complex, ATLAS internal note, ATL-DAQ-2000-021 (2000)
11. The UK ROBin, a prototype ATLAS read-out buffer input module. ATLAS internal note, ATL-DAQ-2000-013 (2000)
12. D Calvet et al., A Read-Out Buffer Prototype for ATLAS High Level Triggers, NSS 2000 Paper 893
13. O. Brosch et al., MicroEnable - a reconfigurable FPGA coprocessor, Proc. 4th Workshop on Electronics for LHC Experiments, Rome Italy (1998), 402-406, CERN/LHCC/98-36
14. A scheme of read-out organisation for the ATLAS high-level triggers and DAQ based on ROB complexes, ATLAS internal note, ATL-DAQ-2000-014 (2000)
15. A prototype RoI builder for the second level trigger of ATLAS implemented in FPGAs, ATLAS internal note, ATL-DAQ-99-016 (1999)
16. K. Kornmesser et al., ATLANTIS - a hybrid approach combining the power of FPGA and RISC processors based on CompactPCI, International Symposium on Field Programmable Gate Arrays, Monterey, California, February 1999
17. Global pattern recognition in the TRT for B-physics in the ATLAS trigger, ATLAS internal note, ATL-DAQ-99-012 (1999)
18. LVL2 full TRT scan feature extraction algorithm for B-physics performed on the hybrid FPGA/CPU processor system ATLANTIS: Measurement results, ATLAS internal note, ATL-DAQ-2000-012 (2000)
19. An integrated system for the ATLAS high level triggers; concept, general conclusions on architecture studies, final results of prototyping with ATM, ATLAS internal note, ATL-DAQ-2000-011 (2000)
20. J. Bystricky et al., Studies of ATM for ATLAS High Level Triggers, DAQ 2000 Workshop, NSS 2000 Paper 869.
21. M. Boosten, Fine-grain parallel processing on a commodity platform: a solution for ATLAS, Draft thesis to be submitted to Eindhoven University of Technology, http://home.cern.ch/mdobson/mesh/M Boosten thesis 14 1299.ps
22. Investigation of the performance of 100 Mbit/s and Gigabit Ethernet components using raw Ethernet frames, ATLAS internal note, ATL-DAQ-2000-032 (2000)
23. Modelling Ethernet switches for the ATLAS LVL2 trigger, ATLAS internal note, ATL-COM-DAQ-2000-021 (2000)
24. R. Dobinson et al., Characterizing Ethernet Switches for use in ATLAS Trigger/DAQ, NSS 2000 Paper 863
25. Evaluation of commercial SCI components and low-level SCI software for the ATLAS second level trigger, ATLAS internal note, ATL-DAQ-2000-029 (2000)
26. ATLAS LVL2 trigger SCI demonstrator evaluation report, ATLAS internal note, ATL-COM-DAQ-2000-037 (2000)
27. Implementation of the message passing software layer over SCI for the ATLAS second level trigger test beds, ATLAS internal note, ATL-DAQ-2000-028 (2000)
28. Ptolemy simulation of the ATLAS LVL2 trigger, ATLAS internal note, ATL-COM-DAQ-2000-020 (2000)