Modeling and simulation of a sigma-delta digital to analog converter using VHDL-AMS

2000 IEEE/ACM International Workshop on Behavioral Modeling and Simulation

Volumn , Issue , 2000, Pages 5-9

  Vogels, M ^a   De Smedt, B ^a   Gielen, G ^a  

^a UNIVERSITY OF LEUVEN   (Belgium)

Author keywords

D A conversion; Sigma Delta; VHDL AMS

Indexed keywords

DYNAMIC ELEMENT MATCHING (DEM);

CAPACITANCE; COMPUTER SIMULATION; LOW PASS FILTERS; NORMAL DISTRIBUTION; SIGNAL TO NOISE RATIO; SYSTEMATIC ERRORS;

DELTA SIGMA MODULATION;

EID: 0034593165     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/BMAS.2000.888357     Document Type: Conference Paper

References (7)

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2. "URL:http://www.eda.org/vhdl-ams/."
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4. G. C. Temes, S. Shu, and R. Schreier, "Architectures for Δ∑ DAC's," in Oversampling Δ∑ conveners, pp. 309-322, IEEE Press, 1992.
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