One-shot Reed-Solomon decoding for high-performance dependable systems

Proceedings of the 2002 International Conference on Dependable Systems and Networks

Volumn , Issue , 2000, Pages 390-399

  Katayama, Yasunao ^a   Morioka, Sumio ^a  

^a IBM RESEARCH   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

INTERNET PROTOCOL; REED-SOLOMON DECODING;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; DYNAMIC RANDOM ACCESS STORAGE; ERROR CORRECTION; FAULT TOLERANT COMPUTER SYSTEMS; INTERNET; NETWORK PROTOCOLS;

DECODING;

EID: 0034590431     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICDSN.2000.857567     Document Type: Conference Paper

References (26)

1. R. E. Blahut, Theory and Practice of Error Control Codes, Adison-Wesley, 1984.
2. S. B. Wicker and V. K.Bhargava (eds.), Reed-Solomon Codes and Their Applications, IEEE Press, 1994.
3. T. R. N. Rao and E. Fujiwara, Error-Control Coding for Computer Systems, Prentice Hall, 1989.
4. A. M. Patel, "On-the-fly decoder for multiple byte errors," IBM J. Res. Develop., vol. 30, pp. 259-269, May 1986.
5. W. Wilhelm, "A New Scaleable VLSI Architecture for Reed-Solomon Decoders," IEEE J. Solid-state Circuits, vol. 34, No. 3, pp. 388-396, 1999.
6. S. Kwon and H. Shin, "An Area Efficient VLSI Architecture of a Reed-Solomon Decoder/Encoder for Digital VCRs," IEEE Trans. Consumer Electronics, vol. 43, pp. 1019-1027, 1997.
7. G. Lee, B. Kwuan, S. Lee, J. Jung, S. Nam, Y. Chun, D. Han, K. Park, Y. Choi, D. Cho and J. Lee, "A VLSI Design of RS Codec for Digital Data Recorder," Proc. ASIC Design Workshop, pp. 115-124, 1996.
8. T. Iwaki, T. Tanaka, E. Yamada, T. Okuda and T. Sasada, "Architecture of High Speed Reed-Solomon Decoder," IEEE Trans. Consumer Electronics, vol. 40, pp. 75-81, 1994.
9. M. A. Neifeld and J. D. Hayes, "Error-correction schemes for volume optical memories," Applied Optics, vol. 35, pp. 8183-8191, Dec. 1995.
10. C. L. Chen and L. E. Grosbach, "Fault-Tolerant Memory Design in the IBM Application System/400™," Proc. the 21st International Symposium on Fault-Tolerant Computing, pp. 393-400, June 1991.
11. C. L. Chen, "Symbol Error Correcting Codes for Memory Applications," Proc. the 26th International Conference on Fault-Tolerant Computing, pp. 200-207, June 1996.
12. M. Abbott, et al., "Durable Memory RS/6000™ System Design," Proc. the 26th International Symposium on Fault-Tolerant Computing, pp. 414-423, June 1994.
13. E. Fujiwara and M. Hamada, "Single b-bit Byte Error Correcting and Double Bit Error Detecting Codes for High-Speed Memory Systems," Proc. the 22nd International Symposium on Fault-Tolerant Computing, pp. 494-501, June 1992.
14. L. Spainhower and T. A. Gregg, "G4: A fault-Tolerant CMOS Mainframe," Proc. the 28th International Symposium on Fault-Tolerant Computing, pp. 432-440, June 1998.
15. H. Imai and Y. Kamiyanagi, "A Construction Method for Double-Error Correcting Codes for Application to Main Memories," (in Japanese) Trans. IEICE Japan, J60-D, pp. 861-868, Sep. 1977.
16. G.-L. Feng, X. Wu, and T. R. N. Rao, "New Double-Byte Error-Correcting Codes for Memory Systems," IEEE Trans. Inform. Theory, vol.44, pp. 1152-1163, 1998.
17. I. I. Drummer, "Nonbinary double-error-correcting codes designed by means of algebraic varieties," IEEE Trans. Inform. Theory, vol. 41, pp. 1657-1666, 1995.
18. Y. Katayama, and S. Morioka, "One-shot Reed Solomon Decoder," Proc. the 33rd Annual Conference on Information Sciences and Systems (CISS), March 1999.
19. Y. Katayama, and S. Morioka, "Error Evaluation Algorithm for One-shot Reed-Solomon Decoder," Proc. IEEE Information Theory Workshop, June 1999.
20. S. Morioka and Y. Katayama, "Design Methodology of One-shot Reed-Solomon Encoder and Decoder," Proc. IEEE International Conference on Computer Design, Oct. 1999.
21. I. G. Macdonald, Symmetric Functions and Orthogonal Polynomials, American Mathematical Society, 1998.
22. Y. Katayama, E. J. Stuckey, S. Morioka, and Z. Wu, "Fault-Tolerant Refresh Power Reduction of DRAMs for Quasi-Nonvolatile Data Retention," Proc. IEEE International Symposium on Design and Fault Tolerance in VLSI Systems, Nov. 1999.
23. K. Itoh, Y. Nakagome, S. Kimura, and T. Watanabe, "Limitations and Challenges of Multi-Gigabit DRAM circuits," Symposium on VLSI circuits Dig. Tech. Papers, pp. 2-7, June 1996.
24. S. Uno, T. Yamashita, H. Oda, S. Komori, Y. Inoue, and T. Nishimura, "Leakage Current Observation on Irregular Local PN Junctions Forming the Tail Distribution of DRAM Retention Characteristics, with new Test Structure," Proc. IEEE International Electron Device Meeting Tech. Dig., 6.6.1, Dec. 1998.
25. K. Saino, K. Okonogi, S. Horiba, M. Sakao, and M. Komuro, "Control of Trench Sidewall in Bias ECR-CVD Oxide-Filled STI for Enhanced DRAM Retention Time," IEEE International Electron Device Meeting Tech. Dig., 6.5.1, Dec. 1998.
26. A. Hiraiwa, M. Ogasawara, N. Natsuaki, Y. Itoh, and H. Iwai, "Local-Field-Enhancement Model of DRAM Retention Failure," IEEE International Electron Device Meeting Tech. Dig., 6.7.1, Dec. 1998.