Memory dependence speculation tradeoffs in centralized, continuous-window superscalar processors

IEEE High-Performance Computer Architecture Symposium Proceedings

Volumn , Issue , 2000, Pages 301-312

  Moshovos, Andreas ^a   Sohi, Gurindar S ^a  

^a Northwestern University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DATA STORAGE EQUIPMENT; HIERARCHICAL SYSTEMS; MATHEMATICAL MODELS; SYNCHRONIZATION;

CENTRALIZED CONTINUOUS WINDOW PROCESSORS; MEMORY DEPENDENCE SPECULATION; SUPERSCALAR PROCESSORS;

PARALLEL PROCESSING SYSTEMS;

EID: 0034581197     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (33)

1. A 5ns store barrier cache with dynamic prediction of load/store conflicts in superscalar processors
2. Memory dependence prediction using store sets
3. Performance evaluation of the powerpc 620 microarchitecture
4. The multicluster architecture: Reducing cycle time through partitioning
5. Data speculation support for a chip multiprocessor
6. Apparatus to dynamically control the out-of-order execution of load-store instructions in a processor capable of dispatching, issuing and executing multiple instructions in a single processor cycle
7. Circuit and method for scheduling instructions by predicting future availability of resources required for execution
8. Advanced performance features of the 64-bit PA-8000
9. The 21264: A superscalar alpha processor with out-of-order execution
10. The Alpha 21264 architecture
11. The PowerPC 620 microprocessor: A high performance superscalar RISC processor
12. Value locality and load value prediction
13. Combining branch predictors
14. Dynamic speculation and synchronization of data dependences
15. Streamlining inter-operation communication via data dependence prediction
16. Complexity-effective superscalar processors
17. Critical issues regarding HPS, a high performance microarchitecture
18. Performance simulation of an alpha microprocessor
19. Trace processors
20. Dynamic instruction reuse
21. Instruction issue logic for high-performance, interruptible, multiple functional unit, pipelined computers
22. Multiscalar processors
23. Memory reference tagging
24. The potential for using thread-level data speculation to facilitate automatic parallelization
25. The superthreaded architecture: Thread pipelining with run-time data dependence checking and control speculation
26. Improving superscalar instruction dispatch and issue by exploiting dynamic code sequences
27. Increasing cache port efficiency for dynamic superscalar processors
28. Speculative techniques for improving load related scheduling