CMOS offset phase locked loop for a GSM transmitter

Analog Integrated Circuits and Signal Processing

Volumn 25, Issue 3, 2000, Pages 253-259

  Yamawaki, Taizo ^a   Kokubo, Masaru ^a   Hagisawa, Hiroshi ^b  

^a Central Research Laboratory

^b HITACHI LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

BANDPASS FILTERS; CMOS INTEGRATED CIRCUITS; ELECTRIC POWER SUPPLIES TO APPARATUS; FREQUENCY CONVERTER CIRCUITS; GAUSSIAN NOISE (ELECTRONIC); GLOBAL SYSTEM FOR MOBILE COMMUNICATIONS; INTERFERENCE SUPPRESSION; MIXER CIRCUITS; MODULATORS; PHASE SHIFT KEYING; SIGNAL FILTERING AND PREDICTION; TRANSMITTERS;

DOWN CONVERSION MIXER; DUPLEXER; GAUSSIAN FILTERED MINIMUM SHIFT KEYING; INTERMEDIATE FREQUENCY; OFFSET PHASE LOCKED LOOP; PHASE ERROR; QUADRATURE MODULATOR;

PHASE LOCKED LOOPS;

EID: 0034545849     PISSN: 09251030     EISSN: None     Source Type: Journal    
DOI: 10.1023/A:1008321829627     Document Type: Article

References (16)