SPIRIT: Satisfiability problem implementation for redundancy identification and test generation

Proceedings of the Asian Test Symposium

Volumn , Issue , 2000, Pages 171-178

  Gizdarski, Emil ^a,b   Fujiwara, Hideo ^b  

^a UNIVERSITY OF RUSE   (Bulgaria)

^b NARA INSTITUTE OF SCIENCE AND TECHNOLOGY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

BOOLEAN SATISFIABILITY METHOD (SAT); TEST PATTERN GENERATION (TPG) ALGORITHMS;

BOOLEAN ALGEBRA; COMPUTER AIDED NETWORK ANALYSIS; COMPUTER SIMULATION; ELECTRIC NETWORK SYNTHESIS; LEARNING ALGORITHMS; REDUNDANCY;

COMBINATORIAL CIRCUITS;

EID: 0034497827     PISSN: 10817735     EISSN: None     Source Type: Journal    
DOI: 10.1109/ATS.2000.893621     Document Type: Article

References (22)

1. F.Brglez and H.Fujiwara, "A Neutral Netlist of 10 Combinational Benchmark Circuits and a Target Translator in Fortran," Proc. IEEE ISCAS, 1985, pp. 663-698.
2. F.Brglez, D.Bryan and K.Kozminski, "Combinational Profiles of Sequential Benchmark Circuits," Proc. IEEE ISCAS, 1989, pp. 1929-1934.
3. S.Chakradhar, V.D.Agarval and S.Rothweiler, "A Transitive Closure Algorithm for Test Generation," IEEE Trans, on CAD, vol. 12, No.7, July 1993, pp.1015-1028.
4. E.Gizdarski and H.Fujiwara, "A New Data Structure for Complete Implication Graph with Application for Static Learning", technical report NAIST-1S-TR2000001, January 2000, pp.18, (http://isw3.aist-nara.ac.jp/IS/TechReport2/report/2000001.ps)
5. E.Gizdarski, "Test Pattern Generation using Boolean Satisfiability," Automatica and Informatics, vol-32, No.2, 1998, pp. 33-40.
6. P.Goel, "An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits," IEEE Trans, on Computers, vol. C-30, No.3, March 1981, pp.215-222.
7. H.Fujiwara and T.Shimono, "On Acceleration of Test Generation Algorithms," IEEE Trans, on Computers, vol. C-32, No. 12, Dec. 1983, pp. 1137-1144.
8. I.Hamzaoglu and J.H.Patel, "New Techniques for Deterministic Test Pattern Generation", Journal of Electronic Testing: Theory and Applications, vol.-15, No. 1/2, 1999, pp.63-73.
9. S.Hellebrand, B.Reeb, S.Tarnick and H.J.Wunderlich, "Patter Generation for a Deterministic BIST Scheme," Proc.IEEE/ACM ICCAD, 1995, pp.88-94.
10. M.Henftling, H.Wittmann and K.Antreich, "A Single-Path-Oriented Fault-Effect Propagation in Digital Circuits Considering Multiple-Path Sensitization," Proc. IEEE/ACM ICCAD, 1995, pp.304-309.
11. S.Kundu, L.M.Huisman, I.Nair, V.Iyengar and L.N.Ready "A Small Test Generation for Large Designs," Proc. IEEE ITC, 1992, pp.30-40.
12. W.Kunz and D.K.Pradhan, "Recursive Learning: A New Implication Technique for Efficient Solutions to CAD Problems-Test, Verification, and Optimization," IEEE Trans, on CAD, vol.13, No.9, Sept.1994, pp.1143-1158.
13. T.Larrabee, "Test Pattern Generation Using Boolean Satisfiability," IEEE Trans, on CAD, vol.11, No.l, Jan.1992, pp.4-15.
14. U.Mahlstedt, T.Gruning, C.Ozcan and W.Daehn, "CONTEST: A Fast ATPG Tool for Very Large Combinational Circuits", Proc. IEEE/ACM ICCAD, 1990, pp.222-225.
15. J.Marques-Silva and K.A.Sakallah, "Dynamic Search Pruning Techniques in Path Sensitization," Proc. IEEE/ACM DAC, 1994, pp.705-711.
16. P.Muth, "A Nine-Value Logic Model for Test Generation," IEEE Trans, on Computers, vol.C-25, No.6, June 1976, pp.630-636.
17. J.Rajski and H.Cox, "A Method to Calculate Necessary Assigmnets in Algorithmic Test Generation", Proc. IEEE ITC, 1990, pp.25-34.
18. M.Schulz, E.Trischler and T.Sarfert, "SOCRATES: A High Efficient Automatic Test Pattern Generation System," IEEE Trans, on CAD, vol.7, No.l., Jan. 1988, pp.126-137.
19. P.Stephan, R.K.Brayton and A.L.Sangiovanni-Vincentelli, "Combinational Test Generation using Satisfiability," IEEE Trans, on CAD, vol.15, No.9, Sept. 1996, pp. 1167-1176.
20. P.Tafertshofer and A.Ganz, "SAT Based ATPG Using Fast Justification and Propagation in the Implication Graph," Proc. IEEE/ACM ICCAD, 1999, pp.139-146.
21. M.Teramoto, "A Method for Reducing the Search Space in Test Pattern Generation," Proc. IEEE ITC, 1993, pp.429-435.
22. J.A.Waicukauski, P.A.Shupe, D.J.Giramma and A.Martin, "ATPG for Ultra-Large Structural Designs," Proc. IEEE ITC, 1990, pp.44-51.