Test sequence compaction for sequential circuits with reset states

Proceedings of the Asian Test Symposium

Volumn , Issue , 2000, Pages 165-170

  Higami, Yoshinobu ^a   Takamatsu, Yuzo ^a   Kinoshita, Kozo ^a  

^a EHIME UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

NON-FAULT-DROPPING FAULT SIMULATIONS; STATIC TEST COMPACTION METHOD;

COMPUTER AIDED NETWORK ANALYSIS; COMPUTER SIMULATION; ELECTRIC NETWORK SYNTHESIS; FAULT TOLERANT COMPUTER SYSTEMS; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT TESTING; VECTORS;

SEQUENTIAL CIRCUITS;

EID: 0034497146     PISSN: 10817735     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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