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Volumn , Issue , 2000, Pages 464-467
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Defect screening challenges in the gigahertz/nanometer age: keeping up with the tails of defect behaviors
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Author keywords
[No Author keywords available]
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Indexed keywords
CMOS INTEGRATED CIRCUITS;
COST EFFECTIVENESS;
DEFECTS;
DESIGN FOR TESTABILITY;
FAILURE ANALYSIS;
INTEGRATED CIRCUIT TESTING;
QUALITY CONTROL;
SEMICONDUCTOR DEVICE MANUFACTURE;
SPURIOUS SIGNAL NOISE;
THRESHOLD VOLTAGE;
DEFECT DEVICE INTERACTIONS;
DEFECT SCREENING;
INTERCONNECT REACTANCE;
PARASITIC REACTANCE;
VLSI CIRCUITS;
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EID: 0034482664
PISSN: 10893539
EISSN: None
Source Type: Conference Proceeding
DOI: None Document Type: Conference Paper |
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Times cited : (5)
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References (4)
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