Integrated process modeling methodology and module for sequential multi-layered substrate fabrication using a coupled cure-thermal-stress analysis approach

Proceedings - Electronic Components and Technology Conference

Volumn , Issue , 2000, Pages 1311-1319

  Dunne, Rajiv C ^a   Sitaraman, Suresh K ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; CURING; DIFFERENTIAL SCANNING CALORIMETRY; ELECTRONICS PACKAGING; MULTILAYERS; SEMICONDUCTING POLYMERS; SEMICONDUCTING SILICON; STRESS ANALYSIS; SUBSTRATES; THIN FILMS; VISCOELASTICITY;

CURE THERMAL STRESS ANALYSIS; HIGH DENSITY INTERCONNECT SUBSTRATES; INTEGRATED PROCESS MODELING; PHOTODEFINABLE DRY FILM POLYMER; THERMOMECHANICAL PROPERTIES;

INTEGRATED CIRCUIT MANUFACTURE;

EID: 0034482066     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)