0.6-W 10-Gb/s SONET/SDH bit-error-rate monitoring LSI

IEEE Journal of Solid-State Circuits

Volumn 35, Issue 12, 2000, Pages 1988-1991

  Kawai, Kenji ^a   Ichino, Haruhiko ^a  

^a NTT Network Innovation Laboratories   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

BIT ERROR RATE; FIBER OPTIC NETWORKS; WAVELENGTH DIVISION MULTIPLEXING;

CLOCK INVERSIONS; DEMULTIPLEXING;

LSI CIRCUITS;

EID: 0034481915     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.890313     Document Type: Article

References (5)

1. S. Shioiri, et al., "A 10-Gb/s SiGe bipolar framer/demultiplexer for SDH systems," in ISSCC Tech. Dig., 1998, pp. 202-203.
2. K. Kawai, et al., "A 557-mW, 2.5-Gbit/s SONET/SDH regenerator-section terminating LSI chip using low-power bipolar-LSI design," IEEE J. Solid-State Circuits, vol. 34, pp. 12-17, Jan. 1999.
3. K. Kawai, et al., "250-mW 2.488-Gbit/s and 622-Mbit/s SONET/SDH bit-error-monitoring LSI," IEE Electron. Lett., vol. 35, pp. 914-916, 1999.
4. Y. Yamabayashi, et al., "High-speed regenerator section terminating LSIS," IEE Electron. Lett., vol. 29, pp. 2057-2058, 1993.
5. M. Ugajin, et al., "Very-high fT and fmax silicon bipolar transistors using ultra-high-performance super self-aligned process technology for low-energy and ultra-high-speed LSIs." in IEDM Tech. Dig., 1995, pp. 735-738.