Deception by design: fooling ourselves with gate-level models

IEEE International Test Conference (TC)

Volumn , Issue , 2000, Pages 921-929

  Rearick, Jeff ^a   Maxwell, Peter ^a  

^a AGILENT TECHNOLOGIES   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; APPLICATION SPECIFIC INTEGRATED CIRCUITS; BUILT-IN SELF TEST; CMOS INTEGRATED CIRCUITS; COMPUTATIONAL COMPLEXITY; COMPUTER SIMULATION; FAILURE ANALYSIS; LOGIC GATES; OPTIMIZATION;

AUTOMATIC TEST PATTERN GENERATION; GATE LEVEL MODELS; SINGLE STUCK AT FAULTS;

DESIGN FOR TESTABILITY;

EID: 0034480140     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (13)