Electrical performance improvements on rfics using bump chip carrier packages as compared to standard small outline packages

Proceedings - Electronic Components and Technology Conference

Volumn , Issue , 2000, Pages 439-444

  Horng, T S ^a   Wu, S M ^a   Li, J Y ^a   Chiu, C T ^b   Hung, C P ^b  

^a NATIONAL SUN YAT SEN UNIVERSITY   (Taiwan)

^b ADVANCED SEMICONDUCTOR ENGINEERING INC   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; COMPUTER SIMULATION; ELECTRIC PROPERTIES; ELECTRONICS PACKAGING; EQUIVALENT CIRCUITS; HETEROJUNCTION BIPOLAR TRANSISTORS; MONTE CARLO METHODS; SCATTERING PARAMETERS; SEMICONDUCTING GALLIUM ARSENIDE;

BUMP CHIP CARRIER PACKAGES; THIN SHRINK SMALL OUTLINE PACKAGES;

CHIP SCALE PACKAGES;

EID: 0034478730     PISSN: 05695503     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (0)