Analytical model to study interfacial delamination propagation in a multi-layered electronic packaging structure under thermal loading

Proceedings - Electronic Components and Technology Conference

Volumn , Issue , 2000, Pages 1526-1534

  Hu, Hurang ^a   Xie, Weidong ^a   Sitaraman, Suresh ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DELAMINATION; INTEGRATED CIRCUIT MANUFACTURE; INTERFACIAL ENERGY; MATHEMATICAL MODELS; STRESS INTENSITY FACTORS; THERMAL EFFECTS; THERMAL EXPANSION;

COEFFICIENT OF THERMAL EXPANSION; INTERFACIAL DELAMINATION PROPAGATION; SINGLE LEVEL INTEGRATED MODULE;

ELECTRONICS PACKAGING;

EID: 0034478429     PISSN: 05695503     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (0)