Power exploration for embedded VLIW architectures

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

Volumn 2000-January, Issue , 2000, Pages 498-503

  Sami, Mariagiovanna ^a   Sciuto, Donatella ^a   Silvano, Cristina ^a   Zaccaria, Vittorio ^a  

^a POLITECNICO DI MILANO   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; PIPELINE PROCESSING SYSTEMS; PIPELINES; COMPUTATIONAL COMPLEXITY; COMPUTER SIMULATION; ELECTRIC POWER MEASUREMENT; INTERCONNECTION NETWORKS; VERY LONG INSTRUCTION WORD ARCHITECTURE;

ARCHITECTURAL PARAMETERS; CYCLES PER INSTRUCTIONS; ENERGY MODEL; INSTRUCTION-LEVEL; PIPELINE STAGES; SCALAR PROCESSORS; SYSTEM LEVELS; VLIW PROCESSOR;

VERY LONG INSTRUCTION WORD ARCHITECTURE; COMPUTER AIDED DESIGN;

INSTRUCTION LEVEL ANALYSIS; INSTRUCTION LEVEL ENERGY MODEL; POWER EXPLORATION;

EID: 0034478037     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2000.896522     Document Type: Conference Paper

References (15)

1. A. Chandrakasan and R. Brodersen, "Minimizing Power Consumption in Digital CMOS Circuits, " Proc. of IEEE, 83(4), pp. 498-523, 1995.
2. M. Sami, D. Sciuto, C. Silvano and V. Zaccaria. "Instruction- Level Power Estimation for Embedded VLIW Cores, " CODES 2000: Eighth Int. Workshop on Hardware/Software Codesign, pp. 34-38, San Diego, CA, May 3-5, 2000.
3. V. Tiwari, S. Malik and A. Wolfe, "Power Analisys of Embedded Software: A First Step Towards Software Power Minimization, " IEEE Trans. VLSI Systems, pp. 437-445, Dec. 1994.
4. M. T.-C. Lee, V. Tiwari, S. Malik and M. Fujita, "Power Anal- isys and Minimization Techinques for Embedded DSP Software, " IEEE Trans. VLSI System,, pp. 123-135, Mar. 1997.
5. J. T. Russel and M. F. Jacome, "Software Power Estimation for High Performance 32-bit Embedded Processors, " Proc. of ICCD '98.
6. D. Sarta, D. Trifone and G. Ascia, "A Data Dependent Approach to Instruction Level Power Estimation, " Low Power Design, 1999 Proc. IEEE Alessandro Volta Memorial Workshop on, pp. 182-190, Como, Italy, Mar. 1999.
7. B. Klass, D. E. Thomas, H. Schmit and D. F. Nagle "Modeling Inter-Instruction Energy Effects in a Digital Signal Processor, " Proc. of ISCAS '98.
8. J. Hennessy and D. A. Patterson, "Computer Architecture: A Quantitative Approach, " Morgan Kaufmann Publishers, San Mateo, CA, Second Edition, 1996.
9. K. Masselos et al. "Interaction between Sub-word Prallelism Exploitation and Low Power Code Transformations for VLIW Multimedia Processors, " Low Power Design, 1999 Proc. IEEE Alessandro Volta Memorial Workshop ont pp. 52-60, Como, Italy, March 1999.
10. H. Mehta et al. "Techniques for Low Energy Software, " Proc. of ISLPED-97: ACM/IEEE Int. Symposium on Low Power Electronics and Design, pp. 72-75, Monterey, CA, August 1997.
11. E. Macii, "Sequential Synthesis and Optimization for Low Power", in Low Power Design in Deep Submicron Electron- ics, NATO ASI Series, Series E: Applied Sciences, Vol. 337, Kluwer Academic Publisher, pp. 321-353, 1997.
12. G. Goossens et at. Embedded Software in Real-Time Signal Processing Systems: Design Technologies Proc. of IEEE, Vol. 35, No. 3, March 1997.
13. Trimaran Home Page, http://www.trimaran.org.
14. M. Kamble and K. Ghose, "Analytical Energy Dissipation Models for Low Power Caches, " Proc. of ISLPED-97: ACM/IEEE Int. Symposium on Low Power Electronics and Design pp. 143-148, Monterey, CA, August 1997.
15. H. Corporaal, "Microprocessor Architectures from VLIW to TTA, " John Wiley and Sons, Chichester, England.