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Volumn 2000-January, Issue , 2000, Pages 296-302

Pipeline optimization for asynchronous circuits: Complexity analysis and an efficient optimal algorithm

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; ASYNCHRONOUS SEQUENTIAL LOGIC; BRANCH AND BOUND METHOD; COMPUTER AIDED DESIGN; PIPELINES; COMBINATORIAL CIRCUITS; CONSTRAINT THEORY; LOGIC DESIGN; OPTIMIZATION; POLYNOMIALS; THEOREM PROVING;

EID: 0034477943     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2000.896489     Document Type: Conference Paper
Times cited : (10)

References (18)
  • 1
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    • SHLPA: A high-level synthesis system for self-timed circuits
    • IEEE Computer Society Press, Nov
    • V. Akella and G. Gopalakrishnan. SHLPA: A high-level synthesis system for self-timed circuits. In Proc. International Con$ Computer-Aided Design (ICCAD), pages 587- 591. IEEE Computer Society Press, Nov. 1992.
    • (1992) Proc. International Con$ Computer-Aided Design (ICCAD) , pp. 587-591
    • Akella, V.1    Gopalakrishnan, G.2
  • 3
    • 1542505215 scopus 로고
    • High-level synthesis of asynchronous systems: Scheduling and process synchronization
    • IEEE Computer Society Press, Feb
    • R. M. Badia and J. Cortadella. High-level synthesis of asynchronous systems: Scheduling and process synchronization. In Proc. European Conference on Design Automation (EDAC), pages 70-74. IEEE Computer Society Press, Feb. 1993.
    • (1993) Proc. European Conference on Design Automation (EDAC) , pp. 70-74
    • Badia, R.M.1    Cortadella, J.2
  • 6
    • 0033328531 scopus 로고    scopus 로고
    • Average-case technology mapping of asynchronous burst-mode circuits
    • Oct
    • W.-C. Chou, P. A. Beerel, and K. Y. Yun. Average-case technology mapping of asynchronous burst-mode circuits. IEEE Transactions on Computer-Aided Design, 18(10):1418-1434, Oct. 1999.
    • (1999) IEEE Transactions on Computer-Aided Design , vol.18 , Issue.10 , pp. 1418-1434
    • Chou, W.-C.1    Beerel, P.A.2    Yun, K.Y.3
  • 13
    • 0019058848 scopus 로고
    • Performance evaluation of asynchronous concurrent systems using Petri nets
    • September
    • C. V. Ramamoorthy and G. S. Ho. Performance evaluation of asynchronous concurrent systems using Petri nets. IEEE Transactions on Software Engineering, 6(5):440-449, September 1980.
    • (1980) IEEE Transactions on Software Engineering , vol.6 , Issue.5 , pp. 440-449
    • Ramamoorthy, C.V.1    Ho, G.S.2
  • 15
    • 84949742438 scopus 로고    scopus 로고
    • F. Somenzi is a professor of computer science at the University of Colorado
    • F. Somenzi. Private Communications, 1999. F. Somenzi is a professor of computer science at the University of Colorado.
    • (1999) Private Communications
    • Somenzi, F.1
  • 16
    • 0027677633 scopus 로고
    • Delay-insensitive multi-ring structures
    • Oct
    • J. Sparso and J. Staunstrup. Delay-insensitive multi-ring structures. Integration, the VLSI journal, 15(3):313-340, Oct. 1993.
    • (1993) Integration, the VLSI Journal , vol.15 , Issue.3 , pp. 313-340
    • Sparso, J.1    Staunstrup, J.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.