Event driven simulation without loops or conditionals

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

Volumn 2000-January, Issue , 2000, Pages 23-26

  Maurer, Peter M ^a  

^a University of South Florida   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COST REDUCTION; SCHEDULING; ALGORITHMS; COMPUTER SIMULATION; DATA STRUCTURES; OBJECT ORIENTED PROGRAMMING; QUEUEING THEORY;

COMPUTATION CODES; EVENT PROPAGATION; EVENT-DRIVEN SIMULATIONS; EVENT-DRIVEN SIMULATORS; INTERNAL OPERATIONS; LOGIC SIMULATIONS; SIMULATION PERFORMANCE; SIMULATION RESEARCH;

COMPUTER AIDED DESIGN; LOGIC GATES;

EVENT DRIVE CONDITIONAL FREE; EVENT DRIVEN SIMULATION; MASTER STATE MACHINE; SIMULATION KERNEL; VIRTUAL FUNCTIONS;

EID: 0034477917     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2000.896445     Document Type: Conference Paper

References (9)

1. E. G. Ulrich, "Event Manipulation for Discrete Simulations Requiring Large Numbers of Events, " JACM, V.21, N.9, Sep. 1978, pp. 777-85.
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3. D. M. Lewis, "A Hierarchical Compiled Code Event-Driven Logic Simulator, " IEEE Transactions on Computer Aided Design, Vol 10, No. 6, pp.726-737, June 1991.
4. D. M. Lewis, " Hierarchical Compiled Event-Driven Logic Simulation, " Proceedings ofICCAD-89, pp.498-501.
5. Z. Wang and P. M. Maurer, "LECSIM: A Levelized Event Driven Compiled Logic Simulator, " Proceedings of the 27th Design Automation Conference, 1990, pp. 491-496.
6. M. Heydemann, D. Dure, "The Logic Automation Approach to Accurate Gate and Functional Level Simulation, " Proceedings of ICCAD-88, pp. 250-253.
7. P. M. Maurer, "The Inversion Algorithm for Digital Simulation, " Proceedings of ICCAD-94, pp. 259-61.
8. P. M. Maurer, "The Shadow Algorithm: A Scheduling Technique for Both Compiled and Interpreted Simulation, " IEEE Transactions on Computer Aided Design, V 11, No 12, Sept. 1993, pp. 1411-1413.
9. F. Brglez, Pownall, Hum, "Accelerated ATPG and Fault Grading via Testability Analysis, " ISCAS-85, pp. 695-698.