Proposal of sub 0.1 um SOI MOSFET structure (partial-ground-plane SOI MOSFET) for RF/digital applications

IEEE International SOI Conference

Volumn , Issue , 2000, Pages 96-97

  Nakakubo, Atsushi ^a   Yanagi, Shin ichiro ^a   Omura, Yasuhisa ^a  

^a KANSAI UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

BIPOLAR TRANSISTORS; GATES (TRANSISTOR); SEMICONDUCTOR DOPING; SEMICONDUCTOR JUNCTIONS; SILICON ON INSULATOR TECHNOLOGY; SUBSTRATES;

SHORT CHANNEL EFFECTS (SCE);

MOSFET DEVICES;

EID: 0034472834     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)