A negative conductance voltage gain enhancement technique for low voltage high speed CMOS op amp design

Midwest Symposium on Circuits and Systems

Volumn 1, Issue , 2000, Pages 502-505

  Yan, Jie ^a   Geiger, Randall L ^a  

^a Iowa State University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRIC CONDUCTANCE; ELECTRIC IMPEDANCE; ELECTRIC POTENTIAL; ELECTRIC POWER SUPPLIES TO APPARATUS; ELECTRIC VARIABLES CONTROL; EQUIVALENT CIRCUITS; FREQUENCY RESPONSE; INTEGRATED CIRCUIT LAYOUT; RESISTORS; TRANSCONDUCTANCE;

GAIN BANDWIDTH PRODUCTS; NEGATIVE CONDUCTANCE; NEGATIVE IMPEDANCE COMPENSATION; VOLTAGE GAIN ENHANCEMENT;

OPERATIONAL AMPLIFIERS;

EID: 0034465717     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

1. A fast-settling CMOS amplifier for SC circuits with 90-dB DC gain
2. A precision variable-supply CMOS comparator
3. Linear CMOS transconductance element for VHF filters
4. A CMOS transconductance-C filter technique for very high frequencies
5. Voltage gain enhancement by conductance cancellation in CMOS Op Amps